This invention relates to static random access memory circuits, and more particularly to static random access memory circuits that are especially suitable for such purposes as inclusion on programmable logic integrated circuit devices for programmable control of the configuration of those devices.
One example of a known programmable logic device 500 is shown in FIG. 1. Device 500 may be generally like the programmable logic devices shown and described in Cliff et al. U.S. Pat. No. 5,689,195, which is hereby incorporated by reference herein. Device 500 includes a plurality of regions 510 of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each region includes a plurality of subregions 512 of programmable logic. For example, each subregion 512 may include a four-input look-up table which is programmable to produce a xe2x80x9ccombinatorialxe2x80x9d output signal which can be any logical combination of four input signals applied to the look-up table. Each subregion 512 may additionally include a register (e.g., a flip-flop) for selectively registering (storing) the combinatorial output signal to produce a registered output signal. And each subregion 512 may include programmable logic connectors (xe2x80x9cPLCsxe2x80x9d) for programmably selecting either the combinatorial or registered output signal as the final output signal of the subregion.
A plurality of horizontal interconnection conductors 520 is associated with each row of regions 510 for conveying signals to, from, and/or between the regions in the associated row. A plurality of vertical interconnection conductors 530 is associated with each column of regions 510 for conveying signals to, from, and/or between the various rows. A plurality of local conductors 540 is associated with each region 510 for making selected signals on the adjacent horizontal conductors 520 available to the associated region. PLCs 522 are provided for making programmable connections between selected intersecting conductors 520 and 540. A plurality of subregion feeding conductors 550 is associated with each subregion 512 for applying selected signals on the adjacent conductors 540 (and adjacent local feedback conductors 560 (described below)) to the associated subregion. PLCs 542 are provided for making programmable connections between intersecting conductors 540/560 and 550. The output signal of each subregion 512 can be applied to selected adjacent vertical conductors via PLCs 562 and/or to selected horizontal conductors 520 via PLCs 564. The output signal of each subregion 512 is also made available as a local feedback signal (via a conductor 560) to all of the subregions in the region 510 that includes that subregion. Selected intersecting horizontal and vertical conductors are programmably interconnectable by PLCs 532.
Another example of a known programmable logic device 600 is shown in FIG. 2. Device 600 may be generally like the programmable logic devices shown in Freeman U.S. Pat. No. Re. 34,363, which is also hereby incorporated by reference herein. Device 600 includes a plurality of configurable logic blocks (xe2x80x9cCLBsxe2x80x9d) 610 disposed on the device in a two-dimensional array of intersecting rows and columns of CLBs. Each CLB 610 may include one or two small, programmable, look-up tables and other circuitry such as a register and PLCs for routing signals within the CLB. A plurality of horizontal interconnection conductor tracks 620 are disposed above and below each row of CLBs 610. A plurality of vertical interconnection conductor tracks 630 are disposed to the left and right of each column of CLBs 610. Local conductors 640 are provided for bringing signals into each CLB 610 from selected conductor tracks 620/630 adjacent to each side of the CLB and/or for applying signals from the CLB to selected adjacent conductor tracks 620/630. PLCs 622/632 are provided for making programmable connections between selected intersecting conductors 620/630 and 640. PLCs 624 are provided for making programmable connections between selected conductors segments in tracks 620 and/or 630 that intersect or otherwise come together at the locations of those PLCs.
In programmable logic devices such as those shown in FIGS. 1 and 2, first-in/first-out (xe2x80x9cFIFOxe2x80x9d) chains of static random access memory (xe2x80x9cSRAMxe2x80x9d) cells are commonly used on the device for programmable control of the configuration of the device. For example, the SRAM cells in such FIFO chains may be used to control the logic performed by each subregion 512 or CLB 610 (e.g., by constituting or controlling the data stored in the look-up tables in those components and by controlling the connections made by the PLCs in those components). The SRAM cells in the FIFO chains may also be used to control the connections made by the various interconnection conductor PLCs (e.g., PLCs 522, 532, 542, 562, 564, 622, 624, and 632) on the device. A typical prior art FIFO SRAM chain 10 will now be described with reference to FIG. 3.
In the FIFO SRAM chain 10 shown in FIG. 3, each SRAM cell 20 includes a relatively strong, forwardly directed inverter 22 connected in a closed loop series with a relatively weak, backwardly directed inverter 24. In the absence of a signal passed from above by an NMOS pass gate 14, each inverter 24 is strong enough to hold the associated inverter 22 in whatever state it was left by the most recent signal passed by the pass gate 14 immediately above. On the other hand, each inverter 24 is not strong enough to prevent the associated inverter 22 from responding to any signal passed by the pass gate 14 immediately above.
Programming data is applied to FIFO chain 10 via DATA IN lead 12 at the start of the chain. Initially all of pass gates 14 are enabled by address signals ADDR-1 through ADDR-N. This allows the first programming data bit to pass all the way down the chain (inverted by each successive inverter 22 that it passes through) until it reaches and is stored in cell 20-N. Pass gate 14-N is then turned off by changing the ADDR-N signal to logic 0. The next programming data bit from lead 12 therefore passes down the chain until it reaches and is stored in the cell immediately above cell 20-N (not shown but similar to all other cells 20). The NMOS pass gate 14 above the cell above cell 20-N is then turned off and the next programming data bit is applied to lead 12. This process continues until all of cells 20 have been programmed and all of pass gates 14 have been turned off. Each cell 20 outputs the data it stores via its DATA OUT lead. These DATA OUT signals may be used to control various aspects of the operation of a programmable logic device that includes chain 10. For example, a DATA OUT signal from chain 10 may control a programmable aspect of the xe2x80x9carchitecturexe2x80x9d of the programmable logic device (e.g., which of several available clock or clear signals a register in a subregion 512 (FIG. 1) or a CLB 610 (FIG. 2) responds to). Or a DATA OUT signal from chain 10 may control a programmable aspect of the logic performed by the device (e.g., by being a datum in a look-up table in a subregion 512 or a CLB 610). As still another example, a DATA OUT signal from chain 10 may control an interconnection conductor PLC (e.g., a PLC 522, 532, etc. (FIG. 1), or a PLC 622, 624, etc. (FIG. 2)) on the device.
The contents of chain 10 may be verified by using the ADDR signals to enable pass gates 14 progressively from the bottom up. This allows the data in cells 20 to be read out one after another from the bottom up via VERIFY lead 16.
It will be apparent from the foregoing that in order to program or verify chain 10 each NMOS pass gate 14 must be able to effectively pass both logic 0 and logic 1 signals. When circuit components are made very small (as is becoming possible as a result of on-going advances in the techniques for semiconductor fabrication) and VCC (the power voltage used for logic 1 signals) is accordingly reduced, an NMOS pass gate 14 may not be able to pass a logic 1 signal that is sufficiently strong to overwrite the logic 0 output of the inverter 24 below it unless the pass gate is made undesirably large. Any unipolar MOS (i.e., NMOS or PMOS) pass gate will have this or a similar problem in these circumstances. Thus a PMOS pass gate does not pass logic 0 very well under the above-described conditions that reduce the effectiveness of an NMOS pass gate in passing logic 1. FIFO SRAM chains are therefore becoming less satisfactory for use as the programmable elements in products such as programmable logic devices.
In view of the foregoing, it is an object of this invention to provide improved SRAMs for use on programmable logic devices or in other similar contexts.
It is a more particular object of this invention to provide SRAMs that can be used on programmable logic devices that are made using advanced integrated circuit fabrication techniques and therefore with extremely small circuit components and/or with the intention of using relatively low VCC potential.
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing an SRAM made up of SRAM cells, all of which store a first of two logic states when the SRAM is initialized, and which are individually or specifically addressed during programming mode when it is desired to change the state of an addressed cell to the second of the two logic states. In addition, the address connection of each cell is such that the cell is changed to the second logic state by passing a logic 0 signal through an NMOS pass gate to the cell, or by passing a logic 1 signal through a PMOS pass gate to the cell. Even NMOS pass gates that are too small to reliably pass logic 1 signals pass logic 0 signals perfectly satisfactorily. Similarly, even PMOS pass gates that are too small to reliably pass logic 0 signals pass logic 1 signals satisfactorily.
The data input terminal of each SRAM cell can also be used to verify the contents of the cell after programming. To verify a cell""s contents, a lead that is used to supply data to the cells during programming is charged to the second logic state and then weakly held at that potential. The cell to be verified is then addressed to connect the data input terminal of the cell to the above-mentioned data input lead. If the cell has the first logic state, the cell will not try to discharge the data input lead, which will therefore remain at the second logic potential. On the other hand, if the cell is at the second logic potential, the cell will gradually discharge the data input lead to the first logic potential (although the cell itself will not change from the second logic state to the first logic state). Thus the potential on the data input lead after the foregoing operations can be used to verify the contents of the SRAM cell being tested.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.